1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a three-dimensional (3D) semiconductor apparatus including a plurality of chips stacked therein.
2. Related Art
In order to increase the integration degree of a semiconductor apparatus, a 3D semiconductor apparatus including a plurality of chips stacked and packaged therein has been developed. The 3D semiconductor apparatus including two or more chips stacked in a vertical direction may exhibit a maximum integration degree in the same space.
In order to implement the 3D semiconductor apparatus, various methods may be applied. In one of the methods, a plurality of chips having the same structure are stacked and connected through wires such as metal lines so as to operate as one semiconductor.
Recently, a through-silicon via (TSV) method has been used, in which a plurality of stacked chips are electrically connected through TSVs. In a semiconductor apparatus using TSVs, a plurality of chips are connected vertically through the TSVs. Therefore, the semiconductor apparatus may reduce the package area more than a semiconductor apparatus including a plurality of chips connected through edge interconnections using wires.
FIG. 1 schematically illustrates a memory chip 10 forming a conventional semiconductor apparatus. In FIG. 1, the memory chip 10 includes a memory area 11, a data input/output block 12, a data transmission/reception unit 13, a plurality of channels DQ0, DQ1, DQ2, . . . , DQn−2, and DQn−1, a test pad 14, and a test data transmission/reception unit 15. The memory area 11 includes a plurality of memory cells. The data input/output block 12 is configured to perform a data input/output operation for the memory area 11 through a data input/output line GIO. The data input/output block 12 is connected to the data transmission/reception unit 13 and the test pad 14. The data input/output block 12 is connected to the data transmission/reception unit 13 and configured to receive data inputted through the plurality of channels DQ0, DQ1, DQ2, . . . , DQn−2, and DQn−1 or output data outputted from the data input/output block 12 to the plurality of channels DQ0, DQ1, DQ2, . . . , DQn−2, and DQn−1, during a normal operation. Furthermore, the data input/output block 12 is configured to receive data TDQ<0:m> from the test pad 14 and the test data transmission/reception unit 15 or output data to the test data transmission/reception unit 15 and the test pad 14, during a test operation. During the test operation, the conventional semiconductor apparatus does not use the data transmission/reception unit 13, but uses the test data transmission/reception unit 15 to perform the test operation. Therefore, the conventional semiconductor apparatus could not verify whether or not a defect occurs in the data transmission/reception unit 13.